Systolic architecture structures are known which make it possible to perform linear spatial filtering in a modular and flexible manner. Such structures comprise elementary cells in cascade. Each of them is provided with a register making it possible to impose a delay of a point, a memory capable of storing multiplier coefficients, a multiplier for performing multiplications by these coefficients of the data received and an adder intended for sequentially adding the products obtained to the sum of the products originating from the downstream cells.
Such embodiments will be found in the article “Real-Time Systolic Array Processor for 2-D Spatial Filtering”, by Aboulnasr and Steenaart, IEEE Transactions on Circuits and Systems, Vol. 35, No. 4, Apr. 1988, pp. 451–455 and in the article “High-Speed Architectures for Two-Dimensional State-Space Recursive Filtering”, by Zhang and Steenaart, IEEE Transactions on Circuits and Systems, Vol. 37, No. 6, Jun. 1990, pp. 831–836.